1. Field of the Invention
The present invention relates to a semiconductor device and more particularly to a semiconductor device having a high voltage (HV) device and a low voltage (LV) device on a silicon on insulator (SOI) substrate and a method of making the same.
2. Background of the Related Art
A background art substrate having a thick epitaxial layer can implement a high voltage (HV) breakdown. Because a device can operate at a relatively high voltage by forming a relatively large depletion region with a deep junction depth, an HV device can be formed in the substrate by forming a deep well in the epitaxial layer, using a long drive-in process.
Because diffusion must occur at a temperature of about 1200° C. for at least about 1000 minutes when forming the background art deep well, processing time is unavoidably lengthened and throughput is reduced. Further, since a junction isolation or a self-isolation process is required to isolate an HV trench region (TR) from a low voltage (LV) TR, a chip size must be large, thus causing difficulty in integrating the isolation process with a normal CMOS process.
To address the above-described background art problems, a background art power integrated circuit (IC) technique using a silicon on insulator (SOI) substrate is employed. A SOI power IC does not require a deep junction, and the power IC technique can reduce the chip size by implementing a trench isolation between HV and LV devices. Further, the power IC technique considerably improves a fabrication throughput, and enables integration with the normal CMOS process.
FIGS. 1A through 1D illustrate cross-sectional views of a background art semiconductor device isolation method. FIG. 1A shows a buried insulating layer 3 formed on a semiconductor substrate 1, and a P-type single crystal silicon layer 5 formed on the buried insulating layer 3 by silicon epitaxy, at a thickness of about 500-2000 Å. Next, a pad oxide film 7 is formed on the single crystal silicon layer 5 by thermal oxidation, and a mask layer 9 is formed on the pad oxide film 7 by chemical vapor deposition (CVD) of silicon nitrite.
FIG. 1B shows the mask layer 9 and the pad oxide film 7 being patterned by a photo-etching method to expose the single crystal silicon layer 5. An HV region, an LV region and a field region are accordingly formed, where the field region electrically insulates the HV region from the LV region.
Next, an anisotropic etching process, such as a reactive ion etching method (RIE), is used to form a trench 11 in the single crystal silicon layer 5, using the mask layer 9 as an etching mask. The trench 11 exposes the buried insulating layer 3.
FIG. 1C shows the substrate of FIG. 1B with the mask layer 9 and the pad oxide film 7 removed to expose a surface of the single crystal silicon layer 5. A silicon oxide layer 13 is deposited by CVD on the crystal silicon layer 5 to fill the trench 11. Then, as shown in FIG. 1D, an etchback process, such as RIE or chemical mechanical polishing (CMP), is applied to the silicon oxide layer 13 to expose the single crystal silicon layer 5. As a result, a field oxide film 13 is formed in the trench 11, and the background art semiconductor device isolation method is completed and followed by fabrication of a background art integrated circuit.
FIG. 2 illustrates a cross-sectional diagram of a semiconductor device fabricated on the substrate shown in FIG. 1D. N-type drift regions 15 are formed in the single crystal silicon layer 5 of the HV and LV regions by a single process, and a P-well region 17 is formed adjacent to the N-type drift region 15 of the HV region. Further, gate electrodes 19 having a gate oxide film (not shown) are formed on the single crystal silicon layer 5 in the HV and LV regions, and N-type impurity regions are formed as source S and drain D regions in the single crystal silicon layer 5 at both sides of each gate electrode 19.
An N-type body contact region 21 is formed adjacent to the source region S of the HV region, and a metal field plate electrode 23 is formed on the single crystal layer 5 on the drift region 15 of the HV region. The drain region D of the HV region is separated from the gate electrode 19 of the drift region 15, and the metal field plate electrode 23 is insulated from the single crystal layer 15 and the gate electrode 19.
The background art has various problems and disadvantages. In the background art semiconductor device isolation method, the HV and LV regions are isolated from each other by the trench 11 and the buried insulating layer 3. Thus, conduction of heat generated during the operation of the device is blocked, and a heat accumulation problem results. Additionally, the trench process is complicated by a dielectric isolation (DI) requirement, and the manufacturing cost of the semiconductor device is increased by the required use of an expensive SOI substrate.